Abstract
Supply voltage scaling along with the use of non-volatile memory (NVM) device has proven to be the viable approaches for reducing both static and dynamic power consumption in SRAM's. The non-volatile SRAM has power down mode, however at lower supply voltage, the performance of the cell is affected due to process variations. So, to overcome this issue, this paper presents a 13-transistor process invariant nvSRAM cell. The cell introduces Schmitt Trigger invertor nvSRAM cell structure instead of CMOS inverter in existing cells. This modification provide tolerance to process variations by making the proposed cell operate at the lowest minimum power supply voltage at 6σ failure point in comparison to others, by considering both static and dynamic measure. Also, the proposed cell consumed 33.4X lower leakage power than the existing one at their respective Vmin.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
