Process integration solution for damage-free bevel for deep Si etch applications

Abstract

This paper reports on the process integration solutions to protect wafer bevel during deep Silicon etching (DSiE) process. In DSiE systems with no physical protection of the wafer bevel, the etching species attack the exposed bevel of the wafer. The damage to the bevel leads to yield loss and numerous processing issues. The damaged bevel wafers are very fragile and very susceptible to breakage. In this paper we present two generic approaches that can be applied to integration flow requiring deep Si etch up to 200 to 230 μm deep. We demonstrate these two approaches for silicon lab-on chip (LoC) fabrication. Silicon fabrication technologies allow very accurate, repeatable and reliable system development in bio-medical applications.