Process integration of 20 nm electron beam lithography and nanopatterning for ultimate MOSFET device fabrication

Abstract

An electron beam microscope based lithography system has been used to fabricate transistors with very small active areas and gate lengths. Electron beam exposures are performed after scanning predefined marks arranged in the actual write field, followed by an automatic adjustment of the beam deflection parameters. A placement accuracy of better than 10 nm has been achieved. High resolution features down to 20 nm were obtained using the organic resist calixarene. The optimum resist parameters for different feature widths were evaluated experimentally in advance. Exposure energies were kept below 10 keV in order to minimize radiation damage, increase resist sensitivity and achieve optimum alignment mark contrasts. Nanoetching was performed by a mixture of bromine and chlorine chemistries after pattern transfer into a hard mask and complete resist removal. Lines of 50 nm were transferred into silicon with a selectivity to TEOS of in excess of 300:1.