Study of the fabrication of PHEMTs for a 0.1 μm scale Γ-gate using electron beam lithography: structure, fabrication, and characteristics

Abstract

For millimeter-wave bands, achieving a very small gate length and an extremely low gate resistance is arguably the single most important technology in manufacturing power GaAs-based pseudomorphic high electron mobility transistor (PHEMT) devices with the properties of high power, high reliability, high throughput and low noise. In order to obtain maximum speed performance from a PHEMT, it is not sufficient to simply use higher mobility materials or structures, it is also necessary to minimize the parasitic resistance (gate resistance and source and drain ohmic contact resistances) and device capacitances if the full potential of the high-speed performance and low minimum noise are to be obtained. To minimize these parameters, the fabrication technologies used are electron beam double exposure with resists of a trilayer structure consisting of PMMA/P(MMA–MAA)/PMMA and a double recess with a volume ratio of mixed solutions (50% citric acid/H 2O 2/H 2O, 1:3:1). The best f max performance is, however, expected by combining the offset-gate advantages with small gate–source spacing. Our group has manufactured a 0.1 μm scale Γ-gate with a small gate length by offsetting the gate to source and with a large gate cross section using electron beam lithography for optimization. In this work we report the fabrication of devices of 70 μm unit gate width and two gate fingers with a drain–source saturation current density of 450 mA/mm, an extrinsic transconductance ( G m) of 363.6 mS/mm, a current-gain-cutoff frequency ( f T) as high as 106 GHz and a maximum oscillation frequency ( f max) of 160 GHz.