Abstract

Hot carrier induced degradation of MOS transistors by direct EB (Electron Beam) writing is investigated. A mixture of optical and EB lithography provides a useful method for analyzing the effect of EB irradiation during a specific ER exposure step. Two types of EB resist (positive and negative) are used to examine the effect of the electron beam on an exposed area. When gate patterns are delineated by EB direct writing using negative resist, MOS transistors show large degradation after a DC stress test. The threshold voltage shift of the device with a 14 &mu;C/cm<sup>2</sup> exposure dose reaches 500 mV after a 1000 sec DC stress test. When positive resist is used, the threshold voltage shift is almost the same as that optically fabricated devices. If Al wirings are patterned by EB lithography, the effect of EB exposure on threshold voltage shift is small for both resist types. The deposition energy in the gate oxide during EB exposure is calculated by Monte Carlo simulation. The energy of the electrons irradiated directly on the active layer, not the total deposition energy, shows some relation to the degradation of MOS devices. The dosage must be decreased to decrease the effect of ER irradiation on device degradation. Therefore, toluene soaking treatment is used on positive resist RE5000P. This process makes it possible to use high sensitivity and high contrast positive resist with low EB damage.

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