Process architectures using MeV implanted blanket buried layers for latch-up improvements on bulk silicon

Abstract

Doped buried layers formed by MeV ion implantation are attractive alternatives to expensive epitaxial substrates for controlling latch-up in CMOS devices. Two different process architecture approaches for forming effective buried layers are discussed. P+ Around Boundary (PAB), and a more recent derivative, BILLI, are compared to a Buried Layer/Connecting Layer (BL/CL) architecture, with regards to latch-up resistance, process flexibility, and future scalability. While both architectures have been shown to increase latch-up trigger current on bulk silicon, the BL/CL process provides greater latch-up control and process/device flexibility. Process and device simulations as well as experimental data indicate that a properly chosen set of implants for both n-well, p-well, and buried layer structures can yield latch-up isolation superior to 3 mm epi.