Priority event monitoring for interrupt-driven computer

Abstract

A priority event monitor consisting of a monitor hardware, a small computer system interface (SCSI) bus link, and a host computer and its use are described. The architecture of the monitor hardware and the host and monitor interaction through the SCSI bus are discussed. The monitor uses event logging hardware and first-in first-out (FIFO) buffering for event storage and timestamping, and a direct memory access (DMA) controller and SCSI bus interface for sending the captured events to the host. The monitor is controlled by a local microcontroller. The microcontroller is a Motorola 68HC11 with embedded FORTH, and the FIFO buffers are AMD Am7200-80 FIFO memory. The Logic Devices 53C80 is used for interfacing with the SCSI bus, and application specific integrated circuits (ASICs) are used for the majority of the priority event logging and for the DMA controller. A PS/2 Microchannel machine serves as the host for controlling the monitor and for data storage. >