Abstract
We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.
Highlights
Advances in semiconductor technologies have led to chips with millions of transistors
The experimental setup consists of the combined voltage scaling and gate sizing algorithm implemented in the environment of SIS
According to Algorithm 1, since only gates that do not violate the timing constraints on any path after down sizing or voltage scaling are accepted, there is no need for a post-processing step to resolve nodes with negative slacks
Summary
Advances in semiconductor technologies have led to chips with millions of transistors. From a general point of view, reducing either supply voltage or physical size of a gate, at logic level, leads to a gate delay increase which implies decreased slack time. In this sense, VS and GS can be effective for delay-constrained optimization only if the given circuit has significant timing slack available in some or all of its constituent gates. We propose a fast heuristic for GS and VS which would identify the maximum number of gates for gate sizing or voltage scaling under the delay constraints so that the total power dissipation of the circuit is minimized.
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