Abstract
A synchronous buck converter based multiphase architecture is evaluated to determine whether or not the most widespread voltage regulator (VR) topology can meet the power delivery requirements of next-generation computer processors. The applied analysis methodology relies on accurate device models for circuit simulations, where the power MOSFETs are central due to their primary relevance to power losses. The method is referred to as virtual design loop and aims at optimizing the overall system performance with minimum empirical efforts. This is successfully applied to the development of a power MOSFET technology offering outstanding dynamic and static performance characteristics in the application. From a system perspective, the limits of power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.
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