Power efficient scalable hybrid processor architecture

Abstract

This paper presents a general-purpose power efficient scalable hybrid architecture, that integrates scalar and vector processor architectures together to achieve better performance for both vectorizable and non-vectorizable portions of a program. As many applications require different cost and performance constraints, the scalability of the proposed design offers numerous variants in order to provide the required performance-cost ratios. Scalability is further investigated in terms of size of data elements, length of vector registers and addressing capability. The hybrid approach of integrating a fully capable scalar processor with a vector processor removes the need for inter-processor communication, thereby decreasing the delay associated with it. The goal is not only to reduce the power consumption but also to increase the power efficiency. The proposed architecture adopts several techniques to improve power efficiency, such as limited multithreading capability, compiler based techniques as well as dynamic power management.