Variation-aware voltage island formation for power efficient near-threshold manycore architectures

Abstract

The power-wall problem and its dual utilization-wall problem are considered among the main barriers to feasible/efficient scaling in the manycore era. Several researchers have proposed the usage of aggressive voltage scaling techniques at the near-threshold voltage region, promising significant improvements in power efficiency at the expense of reduced performance values and higher sensitivity to process parametric variations. In this paper, we introduce a variability-aware framework for exploring the potential power-efficiency of the Near Threshold Computing (NTC) under performance constraints. We propose and analyze the usage of fine-grained voltage islands to cope with the increased effect of variability problem in the NTC region. For the considered workloads, we found that the power impact of fine-grained voltage islands formation can be up to 35% for a 128-core chip operating at NTC region, while the adoption of a variability aware technique can bring to a power reduction of up to 43% with respect to a variability unaware technique. Finally, we show that voltage regulator's complexity, in terms of voltage quantization levels, has a very low effect on the power efficiency at NTC, making in that way the usage of voltage islands a feasible solution for copying with variability <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .