Power and Delay Optimization of FinFET based Adiabatic Logic SRAM Cell

Abstract

The present-day scenario, the VLSI field has grown significantly and the restraints on the critical factors such as power, area & speed have tightened to greater extent. The requirement of high speed and low power applications and their efficiency is the need of the hour. The Static Random-Access Memory [SRAM] cell is the most commonly used memory cell for retaining the data until the power supply is active. In this paper we approach to optimize the power and delay constraints of the SRAM cell. The approach uses FinFET technology as well as the Adiabatic Logic approach to meet the required constraints. FinFET based designs proves to be more efficient with faster switching speeds and better power delay product compared to conventional CMOS. The Adiabatic logic further helps in power reduction by using the stored energy. In this paper, the different types of adiabatic logics are applied to SRAM cell designed using 18nm FinFETs to reduce power consumption and delay. It is observed that Efficient Charge Recovery Logic [ECRL] is most optimized in terms of power consumption and Body-Biasing technique is more efficient in terms of delay as it provides faster switching.