Post-Si-CMOS Devices - Scaling FETs to (Beyond?) 10 nm: From Semiclassical to Quantum Models

Abstract

Understanding (and predicting!) the properties of electronic transport in aggressively scaled devices used in VLSI requires a significant departure from 'conventional' approaches used so far which have relied on extrapolations to smaller length scales of models based on bulk band-structure (often a simple 'effective mass') and semiclassical (Boltzmann) transport. In this talk I will discuss some unexpected and controversial aspects of the physics of semiclassical transport and some attempts to study quantum electronic transport in nanometer-scale structures. From the semiclassical perspective, I will discuss how our attempts to scale FETs to the 10 nm length rely on alternatives to conventional Si CMOS sought on the grounds that: 1. Si seems to have reached its technological and performance limits and 2. The use of alternative high-mobility channel materials will provide the missing performance. With the help of numerical simulations here I will argue about the reasons why indeed Si seems to have hit a performance barrier and whether or not high mobility semiconductors can indeed grant us our wishes. The role of long-and short-range electron-electron interactions will be revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues will also be reviewed to see what advantage alternative substrates may bring us. Finally, the well-known 'virtual source model' will be analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length. From a quantum perspective, I will describe a Master equation approach to handle transport within a density-matrix formalism, giving a few examples on how the method (within a simple effective mass approximation) deals with dissipative transport and with the quantum access resistance in double-gate devices in presence of impurity scattering. Finally, I will present our preliminary efforts to go beyond bulk-band simulation embedding quantum transport in an empirical pseudopotential framework. I will give several examples of systems whose band-structure we have investigated: Thin semiconductor bodies (as in UTBSOIs, FinFETs, Double-Gate FETs), hetero-channels (as those employed in III-V MOSFETs and HEMTs), graphene, graphene nanoribbons, semiconductor quantum wires, and carbon nanotubes. Finally, the coupling of the supercell method to the full-band envelope approximation will be discussed, together with the open boundary conditions and scattering process (handled using a Pauli Master equation scheme) required to study transport in nanometer-scale devices.