(Invited) Scaling FETs to 10 nm: Coulomb Effects, Source Starvation, and Virtual Source

Abstract

In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: 1. Si seems to have reached its technological and performance limits and 2. The use of alternative high-mobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit a performance barrier and whether high-mobility semiconductors can indeed grant us our wishes. We discuss the effect of long- and short-range electron-electron interactions in connection with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues is also reviewed to see what advantage alternative substrates may bring us. Finally, the well-known 'virtual source model' is analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.