Abstract
Summary form only given. An increasing number of system-on-chip (SoC) application-specific integrated circuits (ASICs) have more than one embedded processor with a test access port (TAP). A processor's TAP facilitates a hardware interface to a software development/debug tool. The author presents a technique whereby embedded TAPs can be accessed one at a time via a single TAP consisting of four or five pins. No TAP selection pins are required, and the runtime performance of debug software is relatively independent of the number of embedded processors.
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