Test access of TAP'ed and non-TAP'ed cores

Abstract

Core reuse is an emerging IC design style which enables rapid development of highly complex ICs. Reusable circuit cores come in two basic varieties, hard and soft. Hard cores are optimized for area and performance and are not modifiable by the user, whereas soft cores are user modifiable. If soft cores do not contain testability (i.e. scan/BIST), it can be inserted into the core by the user. Hard cores cannot have test features inserted by the user. Hard core providers should therefore include some means of testing the cores to prevent users from having to add testability external to the core, using pin access or scan/BIST collaring for example. In addition to the hard and soft core varieties, cores will be available for reuse with and without IEEE 1149.1 test access ports (TAPs). Non-TAP'ed cores are circuits that don't have the need for a TAP architecture. They may be scan or BIST testable via a simple, instruction-less test interface. Testable, non-TAP'ed cores could be viewed as 1149.1 test data registers that simply plug into an IC's boundary scan TAP domain to be accessed by TAP instructions. IC providers will face a dilemma when ICs contain two or more TAP domains. Various options for solving this dilemma are discussed.