PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process

Abstract

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high −3dB bandwidth at low collector–emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40×40μm2 and 100×100μm2. Optical DC and AC measurements at 410nm, 675nm and 850nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9MHz and dynamic responsivities up to 2.89A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.