PN Junctions Interface Passivation in 22 nm FDSOI for Low-Loss Passives

Abstract

In this paper, GlobalFoundries’ 22 nm fully depleted (FD) SOI process was run on standard and high-resistivity wafers with a designed PN junctions interface passivation solution to counter parasitic surface conduction (PSC) effects. Substrate quality is monitored in terms of effective resistivity ($\rho_{\text {eff }}$) and losses based on on-wafer measurements of coplanar waveguides (CPW), fabricated in either bottom or top metal layers. Several PN patterns are examined and they demonstrate effective passivation of the PSC, region separating the P- and N-doping regions show better performance, which can further be improved applying a reverse PN bias to widen the depletion regions. $50 \Omega \text{CPW}$ line designed with PN interface passivation achieves 0.15 dB/ mm lower propagation losses at 15 GHz than $50 \Omega$ thin-film microstrip line in this technology. Impact of substrate quality on a 5-20 GHz inductor is analyzed by comparing substrates with standard resistivity, high-resistivity with PSC and high-resistivity with PN junction solution, showing an upto 62% improvement in quality factor.