High-resistivity with PN interface passivation in 22 nm FD-SOI technology for low-loss passives at RF and millimeter-wave frequencies

Abstract

In this paper, GlobalFoundries’ 22 nm fully depleted (FD) silicon-on-insulator (SOI) process is run on standard and high-resistivity wafers with a specially designed PN junctions interface passivation solution to counteract parasitic surface conduction (PSC) effects. Substrate quality is evaluated at RF and mm-wave frequencies through the on-wafer measurements of a set of passives: coplanar waveguides (CPW) lines, two inductors and a crosstalk structure. The effective resistivity (ρeff), losses and harmonics generated by the substrate are monitored based on CPW lines measurements, fabricated in either bottom or top metal layers. Several PN patterns are examined and they demonstrate effective passivation of the PSC, enabling ρeff values in the kΩ.cm range (up to ∼6 GHz) and > 100 Ω.cm up to ∼60 GHz. Patterns with intrinsic region separating the P- and N- doping regions show better performance, which can further be improved applying a reverse PN bias to widen the depletion regions. 50 Ω CPW line designed with PN interface passivation achieves 0.22 dB/mm lower propagation losses at 50 GHz than 50 Ω thin-film microstrip line in this technology. Impact of substrate quality on two spiral inductors is analyzed by comparing substrates with standard resistivity, high-resistivity with PSC and high-resistivity with PN junction solution. The high-resistivity substrate with PN junction solution shows an up to 62% and 15% increase in quality factor with respect to the standard substrates for the 5–20 GHz and 30–60 GHz inductors, respectively. Finally, measurements of a crosstalk structure show a strong isolation improvement in crosstalk through the substrate with the PN interface passivation solution.