PLL based ASIC system for DSP real-time analogue interface

Abstract

This paper describes a new all-hardware technique for real-time interface of standard DSP devices to analogue to digital converters (ADCs), and an associated ASIC system that has been designed to implement the technique. The system is based on a double buffer approach and uses a phase-locked loop unit to control its synchronous parts. It is appropriate for real-time implementation of DSP algorithms that use the block processing approach. The double buffer is facilitated by two on-chip 1 k×16 k bit SRAM blocks, as appropriate for a predefined data frame size of 1024 samples. The system facilitates continuous sampling of the incoming analogue signals, via an ADC, and stores the data in one of the RAMs. Concurrently, the DSP retrieves data stored in the second RAM from previous sampling interval, and processes it. The approach eliminates the need for interrupt service and data collection routines and thus alleviates the design burden of real-time DSP systems with regard to software development. It also offers the advantage of utilising the full power of the DSP device and provides faster processing and potentially higher and accurate sampling frequencies. The design described in this paper represents a discrete ASIC solution for the digital core of the system. The digital core may, where appropriate, be integrated into a single SoC solution alongside a DSP core.