An area efficient mixed-signal test architecture for systems-on-a-chip

Abstract

Mixed-signal systems-on-a-chip (SoCs) are tested using the IEEE 1149.4 analog test bus, but the area overhead and test time are high. We present a new mixed-signal SoC test architecture, which uses the circuit components along with design-for-testability (DFT) hardware. Rather than building a custom analog test waveform generator on chip exclusively for testing, we instead stimulate a digital core to generate a digitized version of the analog test waveform at its outputs. We use a functional digital-to-analog converter (DAC) connected to the core's outputs to convert the samples into an analog multi-tone test waveform, for the cascaded analog core. We add a small amount of DFT hardware into the digital circuit to make it generate a more accurate sample set. In this new test architecture, first, the DFT hardware is tested, and then, the DAC is tested for its static and dynamic parameters using the test tones generated from the digital core. Next, the digital core is tested using vectors applied at the primary inputs and, finally, in the analog test mode, the analog tones, generated using the digital core and the DAC, test the cascaded analog core. On five mixed-signal SoCs, the new architecture reduced average test area overhead by 78.6% and test times by 74%, compared to the 1149.4 standard.