Plasma etch and dielectric deposition processes for TSV Reveal

Abstract

Through-Silicon Vias [TSV] offer improved system performance by reducing interconnect length to increase device speeds, and by using stacking to reduce package form-factors and enabling heterogeneous device integration. Via Reveal' [VR] — a sequence of wafer back side process steps — is key to the successful implementation of TSV. After via formation, typically using a via-middle approach, finished CMOS wafers or interposers are temporarily bonded, face-down, to glass carriers. The TSV are then ‘revealed’ using a combination of Si back-grind and plasma etch steps, and then passivated with dielectric. VR processes must maintain acceptably low Total Thickness Variation [TTV] to allow subsequent bonding/stacking steps. Thermal budgets must also be compatible with carrier bonding adhesives — a particular challenge for dielectric deposition. This paper will focus on 300mm plasma etch and low temperature dielectric Plasma Enhanced Chemical Vapour Deposition [PECVD] processes for VR on 300mm substrates.