Precise Control of Poly-Silicon Height by Plasma Etching in FinFET Technology Node

Abstract

The FinFET technology was brought to mass production for several years to replace the planar transistor structures. Critical process control is highly required for better device and yield performance.[1] When IC scale shrinks, the device performance becomes more and more sensitive to its physical dimension, in which the gate height is included. In the HKMG era, the metal gate height control can be traced back to the poly-silicon height control, including the wafer-level uniformity, wafer to wafer, and lot to lot. Our work is focused on the poly-silicon height control with plasma etch process. The gate height uniformity control was already reported in 2017 by inductively coupled plasma (ICP) etching process.[2] In this report, a precise control method from the point view of local height variation within die, surface induced polish process stability and advanced process control of the poly height planarization is discussed by plasma etching process. With an insertion of cap layer, the local poly-silicon height variation can be improved over 40%. A plasma treatment post the cap layer etch-back can reduce the break-through time of poly-silicon process, and thus improve the stability of CMP process as well as the CMP uniformity. An advanced process control of poly-silicon etch back process is implemented. Dynamic process time is dependent on the poly-silicon height post CMP process, which is due to the normal process variation, and 1% of the poly-silicon height variation after poly-silicon etch back is finally realized. This work was partially sponsored by Shanghai Rising-Star Program (B type). The authors would like to thank Tongxun Guo from Lam research for the support of constructive discussion. Reference: [1] C. Auth et al., “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in VLSI Symp. Tech. Dig., pp. 131–132, 2012. [2] Y. Wang et al., “Poly-Si Planarization by ICP Plasma Etch at FinFET Technology”, ECS Trans. 77(3), 71-76, 2017.