Integration challenges of TSV backside via reveal process

Abstract

Through-Silicon Vias [TSV] offer a method to improved electrical signal speeds by reducing interconnect length. Via Reveal - a wafer back side process steps - is key to the successful implementation of TSV. After via formation, finished CMOS wafers or interposers are temporarily bonded with glass carriers. The TSV are will be `Revealed' using include Si back-grind and plasma etch steps, and then passivated with PECVD, finally, use CMP to open Cu pillar. Via reveal processes must maintain acceptably low Total Thickness Variation (TTV) to allow subsequent bonding/stacking steps. Process temperature must lower than carrier bonding adhesives - a particular challenge for dielectric deposition. Data on Silicon etching will show that etch rate > 3.8μm/min, with Cu pillar TTV 116nm/min to 80%. It also have good uniformity and pass electrical test. Dielectric film/Cu CMP process is applied for protrude the backside TSV coplanarly, the shape of backside TSV will be well control by CMP remove rate and end-point detect.