Abstract
In advanced non-planar MOSFETs architecture, the reliability issue is the primary concern by most researchers due to aggravated local self-heating arising from the enhanced active power dissipation inside the device structure. In this work, 3-D quantum-corrected electrothermal (ET) simulation based analysis is performed to have an insight into the self-heating effect (SHE) in ultra-thin junctionless gate-all-around FETs. The effect of quantum confinement on the carrier distribution due to the ultra-thin channel region is also considered. Through coupled hydrodynamic and thermodynamic carriers transport models, we demonstrate the influence of SHE on the drive current capability, negative output conductance and reliability of the device structure. The ET simulation results also establish the fact that the thermal contact resistance (R th ) strongly influence the device lattice and carriers temperature and the overall performance of the device. Finally, the reliability issues or degradation mechanism of SHE with on-chip ambient temperature variations has also been investigated.
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