Abstract
The dielectric pocket gate-all-around (DPGAA) MOSFET is being considered the best suited candidate for ULSI electronic chips because of excellent electrostatic control over the channel. However, the phenomena of self-heating and hot carrier injection (HCI) severely affect the performance of the device, and make the behaviour of the DPGAA FET very unpredictable. In the present article, a comprehensive investigation under the influence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (VGS). In order to analyse the SHEs, the hydrodynamic (HD) and thermodynamic (TD) transport models have been used for three-dimensional (3D) electrothermal (ET) simulation. The Lucky (hot carrier injection) model has been used to study the HCI degradation in DPGAA MOSFET using Sentaurus 3D TCAD simulator.
Highlights
Under the arena of nanoscale CMOS technology, the gate-all-around (GAA) MOSFET is one of the most promising devices
It be observed that TCmax and TLmax increase gradually up to 0.1V of VDS owing to lowfield transport (LFT) mechanism
It may be noted that enhancement in carrier temperature results in phonon emission, where a significant portion of the generated phonons correspond to optical modes or acoustic modes
Summary
Under the arena of nanoscale CMOS technology, the gate-all-around (GAA) MOSFET is one of the most promising devices. Park et al [17] studied the ET effects and degradation of drain current in GAA MOSFETs with vertically stacked multiple silicon-based nanowire channels. Asheghi et al [21] calculated the degradation in thermal conductivity due to the phonon-boundary scattering in terms of a simple mathematical model It revealed the excessive drain current degradation due to SHEs in Silicon-based GAA MOSFETs. A. S. Banchhor et al [25] analysed that SHE causes zero temperature coefficient (ZTC) bias-point instability in SOI-FINFETs. To date, the influence of ambient temperature (TA), Drain voltage (VDS), and device parameters such as spacer length, spacer conductivity, device length, and thermal contact resistance on carrier temperature, lattice temperature, along with hot carrier injection (HCI) induced degradation of DPGAA FET has not been investigated in detail.
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