Abstract
Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.
Highlights
Multi-gate MOSFET architecture like FinFETs, Tri-gate, and Gate-all-around (GAA) nanowire FETs are regarded as the viable option to continue the aggressive downscaling of CMOS technology down under to 22nm thereby sustaining Moore’s law-driven scaling and International Technology Roadmap for Semiconductors (ITRS) roadmap [1]
In conclusion, we have demonstrated that the interaction of carriers with the phonon generated inside the channel region leads to self-heating effects (SHEs) which gives rise to severe electrothermal issues such as hot carrier injection (HCI) degradation, ambient temperature variations, intrinsic delay, etc
The carriers’ dynamics and the lattice temperature are strongly influenced by the geometrical confinement of the carriers in the ultra-thin channel region of the device
Summary
Multi-gate MOSFET architecture like FinFETs, Tri-gate, and Gate-all-around (GAA) nanowire FETs are regarded as the viable option to continue the aggressive downscaling of CMOS technology down under to 22nm thereby sustaining Moore’s law-driven scaling and ITRS roadmap [1]. In order to have a balance between high performance and device density over the chip area, siliconnanotube based double gate all around (DGAA) MOSFET with core-shell architecture was introduced by Fahad et al in 2011 [4] This 3-D device architecture having channel wrapped around by both inner and outer gates render effective charge control inside the channel region providing excellent immunity to short channel effects (SCEs) as well as enhanced output drive current capability owing. Semi-classical analysis for SHE has been done for other devices in the past [14], but they are not applicable to deal with the ultra-thin device whose behavior is dominated by quantum confinement effects (QCEs) [17] Due to this QCEs, the thermal conductivity of the channel region (silicon) is much lower than the source/drain region (because of phonon confinement and boundary scattering) [18].
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