Performance of heterostructure FET's in LSI

Abstract

This paper reports a comparative evaluation of circuits based on heterostructure field-effect transistors (HFET's) for delay, noise-margin and power dissipation in unloaded and loaded configurations. n-channel enhancement/depletion (E/D) circuits operating at 300 and 77 K and complementary circuits operating at 77 K are compared with respect to each other. The paper also shows that a modified short-channel MOSFET model gives good agreement with experimental behavior of the devices and is adequate for evaluation. Fan-in (FI) sensitivities of delay are much smaller than fan-out (FO) sensitivities of delay for E/D circuits because of capacitive effects. E/D circuit delays are more fan-out sensitive at 300 K than at 77 K because of lower current capability. The fan-in sensitivity of the delay of complementary circuits is larger and is comparable to that circuit's fan-out sensitivity. Under loaded conditions (FI is 3, FO is 3, capacitance is 0.1 pF) at 77 K, 0.5-µm gate length E/D structures show gate delays near 50 ps and 1.0-µm gate length show gate delays near 75 ps. The circuits at 300K exhibit a doubling of the gate delay. The complementary circuits offer, at 77 K, a performance of 70 ps at 0.5-µm gate length and 140 ps at 1.0-µm gate length. The significant performance improvements of complementary circuits with reduction of gate lengths to submicrometer dimensions occurs primarily due to reduction in the device capacitances and secondarily due to improvement of current characteristics. They demonstrate noise margins that are more than 50 percent better than their E/D counterpart along with lower power dissipations. The larger noise margin may be a significant advantage because the small logic swings require stringent parasitic resistance and threshold voltage control.