Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28 nm Node and Beyond

Abstract

With continuous shrinkage of advanced ultralarge scale integrations (ULSI), the impact of line resistance on the devices has become more and more important. In order to achieve low resistance and high reliability of Cu interconnects, we have applied a thin Ti-based self-formed barrier layer using Cu–Ti alloy seed to 45 nm node dual-damascene interconnects and evaluated its performance. The microstructure analysis by transmission electron microscope and energy dispersive X-ray fluorescence spectrometer has revealed that 2-nm-thick Ti-based barrier layer is self-formed at the interface between Cu and low-k dielectrics. The line resistance and via resistance decrease significantly, compared with those of conventional Ta/TaN barrier system. The stress migration performance is also drastically improved using self-formed barrier process. These results suggest Ti-based self-formed barrier process is one of the most promising candidates for advanced Cu interconnects.