Performance improvement of Maneatis PLL for microprocessor clock

Abstract

This paper describes the studies comparing the performance of a traditional single loop Maneatis Phase Lock Loop (PLL) and a proposed Modified Maneatis PLL. The traditional single loop Maneatis PLL is well known for its robustness to supply noise, substrate noise, and possesses variations. In addition, it also exhibits a wide range of operating frequencies. Due to these features, over the years, it had become a default choice for clock generation in many microprocessors. In today's scenario, most of the multi core processor architectures are operated with a selectable combinations supply voltage and operating frequencies and with the rapid switching between different selections. Though the original Maneatis PLL is still being widely used with hardly any modification in this context too, it is becoming imperative to take a relook at the performance of these PLL designs with regard to capture time, capture transients (frequency overshoot or undershoot) and jitter. This paper proposes a modified dual loop Maneatis PLL architecture, which, while inheriting all the key benefits of the traditional Maneatis single loop PLL, also possesses certain additional desirable features. Detailed simulations have been carried out in 0.18µm CMOS technology comparing the performance of the original and proposed modified dual loop Maneatis PLLs. The results show that the proposed scheme has better jitter performance, almost no frequency overshoot or undershoot during the capture transient, and a reduced frequency lock time.