Abstract
The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.
Highlights
The well proven self biased adaptive bandwidth Phase Locked Loop (PLL) [1] considers supply and substrate noise as the dominant sources that lead to timing uncertainties of the output clock
The traditional self biased PLL was designed with the optimum device dimensions of Voltage Controlled Oscillator (VCO) and charge pump functional blocks determined using PNoise analysis in Cadence for reduced jitter performance
The jitter performance of the dual loop is compared with the jitter reduced traditional self biased PLL employing a high KVCO for the required capture range
Summary
The well proven self biased adaptive bandwidth PLL [1] considers supply and substrate noise as the dominant sources that lead to timing uncertainties of the output clock. Its architecture and loop parameters were optimally designed to make the output clock immune to these noise sources. Its loop parameters are process insensitive, and the system becomes process technology independent. These unique features of the self biased PLL ideally are suited for microprocessor clock generation and it has been used for this purpose for nearly two decades [2]-[4]. In today’s scenario of tiled and multi core processers, this well proven PLL architecture operates in
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