Abstract
Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.
Highlights
The revolution in semiconductor industry have resulted in producing modern compact, smart and intelligent electronic devices where performance of microelectronic circuits plays crucial role [1,2,3,4,5,6,7,8,9,10]
The proposed design contains static CMOS logic in the output terminals, advantages of the conventional design remain unchanged in the proposed design
A modified hybrid 4-bit Carry Look-Ahead Adder (CLA) adder has been proposed in this research work
Summary
The revolution in semiconductor industry have resulted in producing modern compact, smart and intelligent electronic devices where performance of microelectronic circuits plays crucial role [1,2,3,4,5,6,7,8,9,10]. Optimization of performance parameters of integrated circuits is a must. Arithmetic Logic Unit (ALU) of modern integrated circuits are responsible for binary arithmetic operations which need to be efficient [11]. Adding binary numbers in one of the key operations of ALU [12]. Performance optimization of adder circuit would bring about overall impact on the performance of ALU [16]. Researchers and academicians are continuously working on developing and implementing new adder designs for better performance [17]
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