Abstract
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.
Highlights
Steep subthreshold slope tunnel FET (TFET), which utilizes the band-to-band tunneling as the conduction mechanism, is one of the most promising candidates for ultra-low voltage/power applications [1].Recent research works on TFET-based circuits have shown significant performance improvement and power reduction at low operating voltage [2,3,4]
We investigate and compare the impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET Ion, Ioff and
Our studies indicate that considering WFV, FinFET has comparable Ion and Ioff variability while TFET has smaller
Summary
Steep subthreshold slope TFET, which utilizes the band-to-band tunneling as the conduction mechanism, is one of the most promising candidates for ultra-low voltage/power applications [1]. Recent research works on TFET-based circuits have shown significant performance improvement and power reduction at low operating voltage [2,3,4]. We provide an in-depth physics-based assessment on the impacts of WFV and fin LER on TFET and FinFET devices including the detailed comparative analyses on Ion, Ioff, and Cg using three-dimensional atomistic TCAD simulations. To assess the variability on large logic circuits, we build look-up table based Verilog-A models, and examine the variability of TFET- and FinFET-based 32-bit CLA circuits using HSPICE simulations with Verilog-A model calibrated with TCAD simulation results. Our work provides in-depth physics-based understanding on the variability of 32-bit CLA circuits and fundamental guidelines on the implementation of TFET-based large logic circuits considering variability
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