Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks

Abstract

Modern System-on-Chip (SoC) designs are faced with many challenges among which efficient communication managing is one of the most important. On-chip communication architectures can have a strong impact on the performance of SoC designs. The traditional SoC interconnects, cannot keep up with the high demands of today's SoC. To address this problem, SoC makers propose new protocols to implement high performance data transfer. AMBA AXI4, is one of the widely used protocols as on-chip bus in recent Wireless Sensor Network SoCs. It includes three distinct interconnect protocols: stream, burst and lite. In this paper, we highlight the various parameters that must be taken into consideration to select the adequate interface for a given application. We analyze and compare the on-chip interfaces for hardware/software (HW/SW) communication when various code transformations are applied on the Zynq-7000 Xilinx platform. Many experiments have been conducted to evaluate the communication between the main processor and the reconfigurable hardware accelerators.