Performance evaluation of the low-voltage CML D-latch topology

Abstract

In this paper, the low-voltage CML D-latch topology is analyzed and compared to the traditional implementation to evaluate its speed potential and power efficiency, which are crucial aspects in current applications. To this end, an analytical delay model is first derived and then used to optimize its speed performance and understand its power-delay interdependence. The delay model, based on the approach proposed by Alioto and Palumbo (IEEE Trans. Circuits Systems I 46(11) (1999) 1330; IEEE Trans. Circuits and Systems II 47(5) (2000) 452), leads to simple expressions that are suitable for pencil-and-paper evaluations. The accuracy of the expressions obtained is tested by comparison to SPICE simulations, by using a bipolar process whose npn transistor has a transition frequency of 20 GHz. The delay expressions derived are used to design and compare the low-voltage and the traditional D-latch both in terms of delay and power-delay tradeoff, by considering a high-performance and a low-power consumption design target. The analytical comparison carried out is general, since it does not depend on the specific bipolar process considered. Analysis shows that the low-voltage D-latch topology does not necessarily allow for a power saving or a better power efficiency, and applications where this topology exhibits some advantage over the traditional implementation are identified.