Modelling and design considerations on CML gates under high-current effects

Abstract

In this paper, the effect of the transit time degradation of bipolar transistors on the power-delay trade-off in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high-speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18(9):1369–1375; Model and Design of Bipolar and MOS Current—Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed-form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power-delay trade-off by considering the effect of the transit time degradation in high-speed designs. In particular, the cases where such effects can be neglected are identified, to better understand how the transit time degradation affects the performance of CML gates for current bipolar technologies. The proposed model has a simple and compact expression, thus it turns out to be suitable for pencil-and-paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20-GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions. Copyright © 2005 John Wiley & Sons, Ltd.