Performance evaluation and read stability enhancement of SRAM bit-cell in 16nm CMOS

Abstract

Read stability is one of the most important factors for designing efficient SRAM cell. This research presents in-depth understanding of 6T-SRAM cell's functionality and comparative performance study of the bit-cell under three different technology nodes of 32nm, 22nm and 16nm. Measures are taken to mitigate the effect of drastic reduction in Read-Static-Noise-Margin at 16nm CMOS technology by implementing the 8T-SRAM structure. To design a SRAM cell, in the present research, read and hold stability are taken into consideration. Then static noise margins are estimated for hold and read operations by meticulously selecting the cell-parameters. The cell ratio has highly impacted on the operation of the memory cell. Temperature dependence is also analyzed for 6T and 8T cell at 16nm technology. HSPICE simulation software is employed and a set of transistors incorporating high-k/metal gate from PTM high performance models are used in this research.