A low voltage and process variation tolerant SRAM cell in 90-nm CMOS

Abstract

In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.