Performance assessment of dual material vertical TFET based on staggered heterojunction of GaSb-Si

Abstract

In this research paper, a new III/V–Si-based TFET is proposed. This device benefits from a doping-less tunneling junction. By using a vertical structure, the issue of scaling is effectively addressed. Instead of using inductive metal, a cladding layer is utilized in our device, which turns the intrinsic source into a p+ region. This helps to overcome the challenges related to silicide formation. We use the Silvaco ATLAS simulator to conduct all the numerical simulations. The impact of defect-related mechanisms on our device performance is thoroughly evaluated. We demonstrate that implementing a large underlap between the gate and drain region in a vertical configuration can effectively solve ambipolar conduction. Parameters such as Ion = 10.1 μA/μm, Ion/Ioff = 1.1 × 1011, and fT = 50.1 GHz at VGS = 0.5V indicate that our device is an excellent option for low-power applications.