Masked ion beam lithography for submicrometer-gate-length transistors

Abstract

GaAs metal-semiconductor field-effect transistors (MESFETs) with 0.3-μm gate length were fabricated using masked ion beam lithography (MIBL). Since MIBL allows submicrometer features to be patterned in thick layers of polymethylmethacrylate (PMMA), a new self-aligned technique was developed. The submicrometer gate as well as the source and drain patterns were defined in PMMA by MIBL and were transferred to the underlying SiO2 film by reactive ion etching. The high aspect ratio structure, formed in the combined PMMA and SiO2 layers used to define the submicrometer gate, allows Ohmic metals to be deposited only in the source and drain regions and not in the gate region via shadow evaporation. The rest of the patterning for contact pads, device isolation, and T-gate overlay was done by optical lithography. The device fabrication process for GaAs MESFETs is presented and the electrical characteristics of these devices are analyzed. The fabricated devices have 0.3-μm gate length and a transconductance of 150 mS/mm. The effects of ion radiation on the device performance is studied. With a 150-nm SiO2 layer between the PMMA and the GaAs substrates, proton induced damage can be removed by thermal annealing at 450 °C for 5 s or by wet etching 50 nm of the top GaAs surface.