Performance analysis of synchronous multibuffered packet-switching networks

Abstract

In this paper, a general mathematical method for analysis of synchronous multibuffered packet-switching interconnection networks in multiprocessor systems is presented. The proposed mathematical method is general in that he analyzed synchronous interconnection networks under uniform and nonuniform traffic. The existing methods for analysis of buffered interconnection networks have assumed either single or infinite buffers at each output (or input) port of a switch, as well as uniform traffic pattern of the networks. Recently, H. Yoon et al. [1] have presented an analytical model of buffered delta networks, assuming finite buffers at each input port and uniform traffic. Firstly, in the paper, a general model of synchronous buffered switching element, using output buffering, under assumption of finite buffer size for a very general class of traffic, is presented. Traffic can be uniform or nonuniform. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for entire network under this assumption. Analytical results obtained with proposed model are then compared with each other, and it is shown that the proposed mathematical method is more general then the known models of interconnection networks.