Performance Analysis of Multibuffered PacketSwitching Networks in Multiprocessor Systems

Abstract

We present a new analytic model and analytic results for the performance of multibuffered packet-switching interconnection networks in multiprocessor systems. Previous analyses of buffered interconnection networks in the literature have assumed either single or infinite buffers at each input (or output) port of a switch. As far as multibuffered interconnection networks are concerned, only some simulation results for delta networks have been known [1]. We first model single-buffered delta networks using the state transition diagram of a buffer. We then extend the model to account for multiple buffers. The analytic results of multibuffered delta networks are compared to simulation results. We also analyze the performance of multibuffered data manipulator networks to demonstrate the generality of the model.