Performance analysis of multi-buffered packet-switching networks in multiprocessor systems

Abstract

In this paper, we extend Jenq [1]'s performance analysis method of single-buffered banyan networks, to be applicable for the multi-buffered packet-switching interconnection networks in multiprocessor systems. Earlier analyses on the buffered interconnection network performances assumed either single or infinite buffers at each input (output) port of a switch. As far as the multi-buffered interconnection network is concerned, only some simulation results for the delta networks have been known [2].We first model the performance of the single-buffered delta networks using the state transition diagram of a buffer. We then extend the model to account for the multiple buffers.The results of the multi-buffered delta networks obtained through this analytic approach are compared with the known simulation results. We also show the state equations for the multi-buffered data manipulator networks to demonstrate the generality of the model.