Abstract
Performance Analysis of MAC Unit using Booth, Wallace tree, Array and Vedic multipliers
Highlights
Recent advances in communication and multimedia systems have resulted in a demand for efficient and fast digital signal processing systems
Analyzing and comparing these multipliers based on power consumption, the delay incurred and area occupancy can help identify the optimum multiplier to be used in the MAC unit
The Multiply Accumulate Unit is designed using four different multipliers in Verilog HDL, simulated and synthesized in Xilinx Vivado. These designs are compared in terms of delay incurred, power consumption and FPGA ultilisation parameters
Summary
Recent advances in communication and multimedia systems have resulted in a demand for efficient and fast digital signal processing systems. Convolution, polynomial evaluation, and dot-matrix operations are some of the processes involved in processing signals digitally. These operations usually involve multiplication and addition and are performed by the Multiply and Accumulate(MAC) unit. The area occupancy, power consumption, and delay incurred in the MAC unit can influence the overall performance of the system. The delay incurred in DSP systems is mainly due to long multiplication processes in the multiplier. Booth, array and Wallace tree multipliers are some of the multipliers that are being widely used Analyzing and comparing these multipliers based on power consumption, the delay incurred and area occupancy can help identify the optimum multiplier to be used in the MAC unit
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