Performance analysis of Cu/CNT-based TSV: impact on crosstalk and power

Abstract

This paper presents a new approach to implement a compact resistance–inductance–capacitance–conductance (RLCG) model for carbon nanotube (CNT) and Cu-based differently shaped through-silicon vias (TSVs) in 3-D ICs. The model primarily comprises the effect of bump, inter-metal dielectric, and eddy currents. Using the proposed model, a mathematical formulation for the coaxial-, cylindrical-, and tapered-based via parasitics is derived using the concept of partial inductance, sectioning the via laterally into infinitesimally thin slices and triangular inter-tube assemblage, respectively. The analytical model is validated against fabrication-based experimental results and subsequently employed for crosstalk-induced delay, peak noise, and power losses analysis. Additionally, for the further validation, the S parameter for the Pi-based model is derived, and compared with an electromagnetic simulator to benchmark the proposed model. The consistency between the analytical and EM simulation-based results further confirms the validity of the proposed model. A significant improvement in the power losses, crosstalk, and peak noise can be observed using the CNT-based tapered TSV compared to the Cu-based via structures. Additionally, it is shown that, irrespective of via height, the average crosstalk-induced delay, peak noise, signal transmission, and reflection loss of the TSV with tapered-shaped 15-shell CNT bundle are reduced by 22.82, 27.80, 47.63 and 33.71%, respectively, compared to the Cu.