Performance Analysis of 16 bit Adders in high speed computing applications

Abstract

The modern day of communication world mainly focus on developing a highly organized architecture to perform high speed computation with minimum power consumption. The various architectures was developed to support computation in the fields like signal processing, data path communications, control and monitoring applications. To perform the high speed computation the architecture of Arithmetic logic unit (ALU) should be well organized in a manner to reduce power, area & propagation delay. The functional block of ALU is adder. This paper elaborates the analysis of different adder structure in terms of VLSI Parameters such as power, area and power delay product. The high speed computation are essential in mixed data processing applications and these computation are developed as blocks of FA to implement 16 bit of operations as a combination of ripple carry adder (RcA),carry skip (CSKA) and bernt kung adder(BkA). Those high speed adders produce the low value of propagation delay when it is implemented using this proposed architecture. The optimized structure of adders are developed by combining the effects of two adders which is functionally differed. The combined functionality of adder based on power & speed of computing The proposed methodology shows that power consumption is reduced by 43%, power delay product by 20.9 % and propagation delay by 46 % compared conventional method of analysis. and also provides the path to identify the effects of critical path delay and reduction it.