Abstract
In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures. In particular, the proposed buried channel array transistor has a 43% lower off current than the conventional asymmetric doping structure. Here, we show the range of the effective buried insulator parameter according to the depth of the buried gate, and we effectively show the range of improvement for the off current.
Highlights
As the dynamic random-access memory (DRAM) cell size decreases, DRAM reduces the size of the line width and length of the gate [1,2]
The saddle-type FinFET has an increased gate induced drain leakage (GIDL) because of its wider overlapped regions of gate and drain compared with the recessed channel array transistors [12]
This paper proposes a structure that is partially isolated in the area below the storage node of the buried channel array transistor (Pi-BCAT) for a DRAM cell transistor of less than 20 nm [18,19,20,21]
Summary
As the dynamic random-access memory (DRAM) cell size decreases, DRAM reduces the size of the line width and length of the gate [1,2]. The continuous reduction in the size of the line width requires a cell size of less than 20 nm, and the high doping concentration increases the GIDL [17] To solve this problem, the existing structure currently being manufactured needs to be improved. This paper proposes a structure that is partially isolated in the area below the storage node of the buried channel array transistor (Pi-BCAT) for a DRAM cell transistor of less than 20 nm [18,19,20,21]. 2b2b shows a Pi-RFinFET with a buried insulator doping region bottom storage node structure [27].
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