Partial dynamic reconfiguration framework for FPGA: A survey with concepts, constraints and trends

Abstract

With demand for high performance and huge logic dense portable devices, the need for silicon area is increasing. A potential solution for the electronics industry to develop such huge logic demanding applications is the ability to reconfigure the system partially without altering the overall system operation. For more than two decades, reconfigurable computing has aided various applications and has seen tremendous technology transformation. The paper presents a survey of reconfigurable computing, its present state of existence, and a detailed report on state of art Partial Dynamic Reconfiguration Framework (PDRF) for reconfiguring FPGA designs partially and dynamically. A detailed analysis of the features, limitations, and performance of a wide range of PDRFs available in the literature are reported.