Parity Codes Used for On-Line Testing in FPGA

P Kubalík,H Kubátová

doi:10.14311/788

Abstract

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented.

Highlights

The design process for FPGAs differs mainly in the “design time”, i.e., in the time needed from the idea to its realization, in comparison with the design process for ASICs
Information redundancy is based on error detecting (ED) codes, and leads either to area redundancy or time redundancy
We designed concurrent error detection (CED) circuits based on FPGAs with a possible dynamic reconfiguration of the faulty part

Summary

Introduction

The design process for FPGAs differs mainly in the “design time”, i.e., in the time needed from the idea to its realization, in comparison with the design process for ASICs. FPGAs enable different design properties, e.g., in-system reconfiguration to correct functional bugs or update the firmware to implement new standards. FPGAs enable different design properties, e.g., in-system reconfiguration to correct functional bugs or update the firmware to implement new standards Due to this fact and due to the growing complexity of FPGAs, these circuits can be used in mission-critical applications such as aviation, medicine or space missions. There have been many papers [1, 2] on concurrent error detection (CED) techniques. Information redundancy is based on error detecting (ED) codes, and leads either to area redundancy or time redundancy. We will assume the utilization of information redundancy (area redundancy) caused by using ED codes

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