Parallel Generation of Most Reliable LLRs of a Non-Binary Symbol

Abstract

The first task of non-binary (NB) decoders [low-density parity check (LDPC) or turbo] is to generate the log-likelihood ratio (LLR) of the received NB symbols defined over Galois fields GF( $q>2$ ). In the extended min-sum decoding algorithm, the intrinsic information associated to a given received symbol is a sorted list of the $n_{m}$ most reliable NB GF symbols along with their associated reliability values. In this letter, we present a fully parallel LLR generation algorithm, an enabler for very high throughput decoding that processes one received symbol per clock cycle. We provide complexity figures for LLR architectures designed over GF( $q$ ) of sizes 64, 256, and 1024, as well as different values of $n_{m}$ . Compared with the related state-of-the-art architecture, field-programmable gate array (FPGA) synthesis results show that the proposed parallel architecture improves the hardware efficiency by a factor ranging from 7 up to 15.